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The object of this activity is to explore a capacitor based circuit which can produce an output voltage which is higher than the supplied voltage. This class of circuits are referred to as DC to DC converters or boost regulators.
The basic concept of capacitor based DC to DC converter is shown below in figure 1. These are often referred to as “flying capacitor” or “charge-pump” voltage converters. The operation alternates between the two configurations shown in figure 1. On the left, switches S1 and S5 are closed connecting C1 between ground and VIN. On the right, switches S4 and S8 are closed connecting C2 between VIN and VOUT. For the half cycle shown capacitor C1 is charged to the voltage at VIN and VOUT is the sum of the voltage at VIN and the voltage on capacitor C2. For the second half cycle the switches are reversed. Now with S2 and S6 closed C1 is connected between VIN and VOUT. Also switches S3 and S7 will now be closed connecting C2 between ground and VIN. So now we can see that after a few cycles VOUT, the voltage across capacitor C3 will be equal to twice VIN. As you can see the capacitors “fly” back and forth between VIN and VOUT, thus the name “flying capacitor”. One can also see that what is in effect happening is the charge on capacitors C1 and C2 is alternately transferred or pumped onto capacitor C3 charging it up to two times VIN. This action gives rise to the second “charge pump” name.
Figure 1 Capacitor based voltage doubler
We will now replace the ideal switches in the diagram with actual electronic switches. There are a number of possible devices that could be used but the MOS FET transistor is most often used. The next diagram shows a direct substitution of NMOS ( S1,S3,S5,S7 ) and PMOS ( S2,S4,S6,S8 ) devices for the switches in the first diagram. It can be noted that switches S1 and S2 form a complementary pair and take the same form as a CMOS inverter logic gate. The other three sets of switches form similar complementary pairs.
Figure 2 CMOS voltage doubler
ADALM2000 Active Learning Module
2 - ZVN2110A NMOS FET (2N7000)
2 - 74HC04 HEX CMOS Inverters (CD4007, CD4069)
2 - 10 uF capacitors
1 - 220 uF capacitor
2 - 1N914 small signal diodes
Small handheld DMM
+5 V bench power supply
The breadboard connections for the first version are as shown in figure 3 below. The DMM should be connected to measure the voltage at VOUT. The +5V bench power supply should be connected to the Vin node. The digital pulse output drives the input of the first Inverter gate at pin 1. Scope input 1+ (single ended) is connected to the drain terminal of M1 and scope input 2+ (single ended) is connected to the drain terminal of M2.
Figure 3 NMOS and Diode DC-DC converter
The digital pulse source output should be configured for a 50% duty cycle and 20 KHz output frequency. The Single ended input of scope channel 1 (1+) is used to measure the waveform seen at the drain of M1 and scope channel 2 (2+) is used to measure the waveform seen at the drain of M2.
Be sure to start up the digital pulse source output on the Analog Discovery Lab board before turning on the +5V bench supply. The boosted output voltage at node VOUT should be observed and should be approximately equal to 2 times the DC value of the bench supply.
What is the voltage on VOUT? Why is it not exactly 2 times VIN?
What is the effect of changing the frequency of the digital pulse output?
Is there a minimum or maximum frequency?
How much current can the circuit supply to a load? Try various resistors as a load.
Is that current affected by the frequency of the digital pulse output?
Calculate the conversion efficiency of the circuit. Ratio of output power (IOUT*VOUT) to input power (IIN* 5V)
Change the value of C1 and C2 and redo the above. How have the results changed?
Connect the other inverters in the 74HC04 package in parallel with INV1 and INV2 in the diagram. What effect do these added drivers have on the results?
The breadboard connections for another version are as shown in figure 4 below. A second package of CMOS inverters is used for the upper set of switches (INV3 and INV4) rather than the discrete FETs and diodes. The ground connection of the second 74HC04 is connected to the VIN node and the supply connection at pin 14 becomes the VOUT node. The DMM should be connected to measure the voltage at VOUT. The +5V bench power supply should be connected to the VIN node. The digital pulse source output drives the input of the first Inverter gate at pin 1.
Figure 4 All CMOS Inverter configuration
Figure 5 shows a configuration that produces VOUT equal to -VIN. The second 74HC04 is connected below ground as shown to produce a VOUT that is equal to -VIN.
Figure 5 Supply voltage inverter.
What sort of circuit could you make to generate the 100 KHz square wave other than using the digital pulse source output on the Analog Discovery Lab board? There are four additional inverters in the 74HC04 package. The other inverters along with RC delay network, R4 C4 can be configured into a ring oscillator as shown below. The values for R4 and C4 are approximate for 100 KHz and can be adjusted as needed.
Figure 6 square wave oscillator
What other types of oscillator circuits might be used to generate the 100 KHz square wave?
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Hex inverter Pinouts:
Figure 7 74HC04 and CD4069 share the same package pinouts
Figure 8 CD4007 CMOS array pinout
As many as three individual inverters can be built from one CD4007 package. The simplest first one to configure as shown below is by connecting pins 8 and 13 together as the inverter output. Pin 6 will be the input. Be sure to connect pin 14 VDD to power and pin 7 VSS to ground.
Figure 9 CD4007 inverter connections
The second Inverter is made by connecting pin 2 to VDD, pin 4 to VSS, pins 1 and 5 are connected together as the output and with pin 3 as the input.
The third inverter is made by connecting pin 11 to VDD, pin 9 to VSS, pin 12 is the output and pin 10 is the input.
Two of these inverters can be used to construct the inverters needed in figure 3.